1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to a dynamic random access memory (DRAM) structure and a method of manufacturing thereof.
2. Description of the Background Art
In recent years, the demand for semiconductor memory devices are rapidly increasing due to the remarkable spread of information equipment of computers. Semiconductor memory devices having large functional storage capacity and capable of high speed operation are required. Accordingly, developments in techniques are carried out regarding high density integration, quick response, and high reliability of semiconductor memory devices.
A DRAM in semiconductor memory devices is known as being capable of random input/output of storage information. A DRAM comprises a memory cell array which is the storage region for storing a plurality of storage information, and a peripheral circuit required for input from and output to an external source. FIG. 6 is a block diagram showing a general DRAM structure. Referring to FIG. 6, a DRAM 50 comprises a memory cell array 51 for storing data signal of storage information, a row-and-column address buffer 52 for receiving external address signals to select memory cells forming a unit storage circuit, a row decoder 53 and a column decoder 54 for specifying a memory cell by decoding the address signal, a sense refresh amplifier 55 for amplifying and reading out the signal stored in the specified memory cell, a data-in buffer 56 and a data-out buffer 57 for data input/output, and a clock generator 58 for generating a clock signal.
The memory cell array 51 occupying a large area on the semiconductor chip has a plurality of memory cells for storing unit storage information arranged in a matrix manner. A one-transistor one-capacitor type memory cell is well known, implemented with one MOS transistor and one capacitor connected thereof. Such memory cells are widely used for large capacity DRAMs because of its simple structure contributing to the improvement in higher integration of the memory cell array.
The memory cells of a DRAM can be classified into several types depending on the structure of the capacitor. A stacked type capacitor can have an increased capacitor capacitance through extension of the major portion of the capacitor to the gate electrode and over the field isolation film to increase the opposing area between electrodes of the capacitor. By virtue of this characteristic, a stacked type capacitor can ensure an enough capacitor capacitance even in the case devices are miniaturized by larger scale integration of the semiconductor device. The extensive usage of stacked type capacitors resulted from such larger scale integration of the semiconductor devices. Toward larger scale integration of semiconductor devices, development in stacked type capacitors are also in progress. A stacked type capacitor of a cylindrical type has been proposed to ensure constant capacitance even in the case where semiconductor devices are integrated in a more miniaturized manner. Such a capacitor is described in "Symposium on VLSI Techn." page 69 (1989). FIG. 7 is a sectional view of a DRAM employing a conventional stacked type capacitor of a cylindrical type. Referring to FIG. 7, the DRAM adopting a conventional stacked type capacitor of a cylindrical type comprises a memory cell array and a peripheral circuit. The memory cell array comprises one transfer gate transistor 3 and one capacitor 10. The transfer gate transistor 3 comprises a pair of source/drain regions 6 formed on the surface of a P type silicon substrate 1, and gate electrodes 4b and 4c formed on the surface of P type silicon substrate 1 between one pair of source/drain regions 6 with a gate insulating film 5 thereunder. The periphery of gate electrodes 4b and 4c are covered by an insulating film 14. A thick interlayer insulating film 16 is formed on the surface of silicon substrate 1 where transfer gate transistor 3 is formed. A capacitor 10 is implemented with a layered structure of a lower electrode (storage node) 11, a dielectric layer 12, and an upper electrode (cell plate) 13. One of source/drain regions 6 forming transfer gate transistor 3 is connected to a bit line 15. A wiring layer 18 is provided corresponding to gate electrodes 4b, 4c, and 4d. The peripheral circuit is implemented with two MOS transistors of identical conductivity type. That is to say, two pairs of source/drain regions 26 forming MOS transistors are provided on the P type silicon substrate. Gate electrodes 24c and 24d with a gate insulating film 25 thereunder are formed between one pair of source/drain regions 26. The MOS transistor formed on P type silicon substrate 1 is device-isolated by a field oxide film 22. Each of the source/drain regions 26 is connected to a wiring layer 38 via a contact layer 36.
A stacked type capacitor has been developed for ensuring constant capacitance where devices are miniaturized in accordance with the increased scale of integration of the semiconductor device. Such a capacitor manufactured by a conventional method has a sectional view of FIG. 7.
This cylindrical stacked type capacitor has the electrode formed vertically upwards from P type silicon substrate 1. There was a problem that a step is formed between the memory cell array and the peripheral circuit due to difference in height of the memory cell array and the peripheral circuit, after the formation process of the electrode. Such a stepped portion will lead to an inconvenience that the focus of the exposed light is offset at the stepped portion at the later photolithography processing. It was difficult to improve the patterning accuracy, with the problem that the processing accuracy could not be improved. There was also a problem that a residue not etched is formed at the stepped portion when etching is carried out. There was also a difficulty in the manufacturing process due to difference in depth between the contacts of the memory cell array and the peripheral circuit, when the contact is formed after the formation of a stacked type capacitor of the cylindrical type.